E
EDA_hg81
Guest
Code:
proces (refclk, reset)
beginnen
if (reset = '1 ') then
vlstart_reg <= (others => '0 ');
fpixclk_reg <= (others => '0 ');
numline_reg <= (others => '0 ');
hpstart_reg <= (others => '0 ');
numapix_reg <= (others => '0 ');
elsif (rising_edge (refclk)) dan
if (tuner = '0 ') then
vlstart_reg <= vlstart;
fpixclk_reg <= fpixclk;
numline_reg <= numline;
hpstart_reg <= hpstart;
numapix_reg <= numapix;
end if;
end if;
einde proces
-------------------------------------------------- ----
proces (refclk, reset)beginnen
if (reset = '1 ') then
tuneack <= '0 ';
tune_state <= idle;
elsif (rising_edge (refclk)) dan
geval tune_state is
wanneer idle =>
tuneack <= '0 ';
if (tuner = '1 ') then
if (updwhvsync (0) = '1 ') then
hpstart_reg <= hpstart_reg - 1;
elsif (updwhvsync (1) = '1 ') then
hpstart_reg <= hpstart_reg 1;
- Elsif (updwhvsync (2) = '1 ') then
- Vlstart_reg <= vlstart_reg - 1;
- Elsif (updwhvsync (3) = '1 ') then
- Vlstart_reg <= vlstart_reg 1;
end if;
tune_state <= wtunef;
end if;
wanneer wtunef =>
tuneack <= '1 ';
if (tunef = '1 ') then
tune_state <= idle;
end if;
wanneer anderen =>
tune_state <= idle;
einde geval;
end if;
einde proces
proces (refclk, reset)
beginnen
if (reset = '1 ') then
vlstart_reg <= (others => '0 ');
fpixclk_reg <= (others => '0 ');
numline_reg <= (others => '0 ');
hpstart_reg <= (others => '0 ');
numapix_reg <= (others => '0 ');
elsif (rising_edge (refclk)) dan
if (tuner = '0 ') then
vlstart_reg <= vlstart;
fpixclk_reg <= fpixclk;
numline_reg <= numline;
hpstart_reg <= hpstart;
numapix_reg <= numapix;
end if;
end if;
einde proces
-------------------------------------------------- ----
proces (refclk, reset)beginnen
if (reset = '1 ') then
tuneack <= '0 ';
tune_state <= idle;
elsif (rising_edge (refclk)) dan
geval tune_state is
wanneer idle =>
tuneack <= '0 ';
if (tuner = '1 ') then
if (updwhvsync (0) = '1 ') then
hpstart_reg <= hpstart_reg - 1;
elsif (updwhvsync (1) = '1 ') then
hpstart_reg <= hpstart_reg 1;
- Elsif (updwhvsync (2) = '1 ') then
- Vlstart_reg <= vlstart_reg - 1;
- Elsif (updwhvsync (3) = '1 ') then
- Vlstart_reg <= vlstart_reg 1;
end if;
tune_state <= wtunef;
end if;
wanneer wtunef =>
tuneack <= '1 ';
if (tunef = '1 ') then
tune_state <= idle;
end if;
wanneer anderen =>
tune_state <= idle;
einde geval;
end if;
einde proces