behoefte aan advies en hulp!

M

mat_jat

Guest
hallo!i, m newbie in dit forum en VHDL programmering ...
dus ik hoop dat iemand mij kan helpen mijn programmering en de juiste
geef me wat advies ..
Ik probeerde om een controle-eenheid tussen de UART-en AES core ...Ik maak een beetje
moddification van de broncode die ik download van open kernen ...
balg is mijn controle-eenheid die ik probeer te schrijven, maar ik weet niet hoe om te controleren dat elk pad ontvangt de gegevens die moeten krijgen ... plz help me- Beta versie

library IEEE;
gebruik IEEE.std_logic_1164.all;
gebruik IEEE.std_logic_arith.all;
gebruik IEEE.std_logic_unsigned.all;entiteit final_aes128 is
port (
RxD: in Std_Logic;
TxD: out Std_Logic;
Reset: in STD_LOGIC;
gedaan: out std_logic;
CLK: in STD_LOGIC

)
einde final_aes128;architectuur final_aes128_arch van final_aes128 is

- AES signalen
signaal AES_start, AES_outrdy, AES_mode, load: std_logic;
signaal AES_DataOut: std_logic_vector (127 Downto 0);
- signaal counter_DataIn, counter_KeyIn: std_logic;

- ontvangen en zenden signaal
signaal UART_Outrdy, UART_Rx, UART_Tx, UART_Tdone, UART_TbufE: std_logic;

- input AES core-signaal
signaal AES_key: std_logic_vector (127 Downto 0);
signaal AES_data: std_logic_vector (127 Downto 0);

signaal UART_DataIn, UART_DataOut: std_logic_vector (7 Downto 0);
signaal En_Encryp: std_logic;

- state signaal
signaal staat: std_logic_vector (3 Downto 0);
signaal sub_state: std_logic_vector (3 Downto 0);component clk_divider
port (
SysClk: in Std_Logic; - System Klok
En_Encryp: out Std_Logic; - Controle signaal
Reset: in Std_Logic - Reset
)

end component clk_divider;component miniUART
port (
DataRdy: out std_logic;
SysClk: in Std_Logic; - System Klok
Reset: in Std_Logic; - Reset-ingang
- CS_N: in Std_Logic;
RD_N: in Std_Logic;
WR_N: in Std_Logic;
RxD: in Std_Logic; - toewijzen pens-naar-W8
TxD: out Std_Logic; - toewijzen pins naar D15
TBufE: buffer std_logic;
TDone: out std_logic;
DataIn: in Std_Logic_Vector (7 Downto 0); - ontvangen uitgang van AES-kern
DataOut: out Std_Logic_Vector (7 Downto 0 ));-- gegevens naar AES core
end component miniUART;component aes128_fast
port (
clk: in std_logic;
reset: in std_logic;
start: in std_logic; - tot inleiding van de encryptie / decryptie-proces na het laden
modus: in std_logic; - om te selecteren encryptie of decryptie
belasting: in std_logic; - het laden van de input en sleutels.
key: in std_logic_vector (127 Downto 0);
data_in: in std_logic_vector (127 Downto 0);
data_out: out std_logic_vector (127 Downto 0);
gedaan: out std_logic);
end component aes128_fast;beginnen

U_clkdiv: clk_divider
poort kaart (Clk, En_Encryp, reset);

U_UART: miniUART
poort kaart (UART_outrdy, Clk, reset, UART_Rx, UART_Tx, RxD, TxD,
UART_TBufE, UART_TDone, UART_DataIn, UART_DataOut);

U_AES: aes128_fast
poort kaart (En_Encryp, reset, AES_start, AES_mode, belasting, AES_key,
AES_data, AES_DataOut, AES_Outrdy);FSM: proces (clk, reset, UART_DataIn, UART_DataOut, UART_Outrdy,
UART_TbufE, UART_TDone,
staat, sub_state, AES_key, AES_Data, AES_Outrdy,
AES_DataOut)

- Status bericht variabelen, met "#" als end-of-line karakter.

beginnen

indien reset = '1 'dan
toestand <= "0 X"; - staat
sub_state <= "0 X"; - substate

UART_Tx <= '1 '; - dataverkeer bl = '0'
UART_Rx <= '1 '; - TRM gegevens bl = '0'
UART_DataIn <= (others => '0');-- duidelijk gegevensinvoer UART
AES_data <= (others => '0 ');
AES_key <= (others => '0 ');
AES_start <= '0 '; - start proces van coderen / decoderen
AES_mode <= '0 '; - signaal mode coderen / decoderen
gedaan <= '0 '; - van boven entiteit
belasting, <= '0 '; - load-toets en gegevens

elsif clk'event en clk = '1 'dan
AES_Start <= '0 '; - disable beginnen coderen / decoderen
UART_Tx <= '1 '; - signaal uitschakelen zenden
UART_Rx <= '1 '; - signaal uitschakelen ontvangen

geval staat
- Stand-by staat, wacht startbit
wanneer X "0" => - wanneer toestand 0
UART_Rx <= '0 '; - in staat stellen te lezen
indien UART_Outrdy = '1 'dan - gegevens klaar om te lezen
als UART_DataOut = X "31" dan - start byte = 1 in Hex
toestand <= staat 1;
gedaan <= '0 ';
elsif UART_DataOut = X "30" dan - verzoek status
staat <= "0 X"; - staat <= "1101"
gedaan <= '0 ';

end if;
end if;

wanneer X "1" => - wanneer toestand 1
indien UART_TBufE = '1 'dan - check buffer leeg
UART_DataIn <= "31 X";
UART_Tx <= '0 '; - in staat stellen gegevens te verzenden
toestand <= staat 1;

end if;

- Ontvang PlainText
wanneer X "2" =>
UART_Rx <= '0 '; - in staat stellen te ontvangen
belasting, <= '1 '; - laden van gegevens
if (UART_Outrdy = '1 ') then - klaar om te lezen
geval sub_state is

wanneer X "0" => - sub_state
AES_data (127 Downto 120) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "1" =>
AES_data (119 Downto 112) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "2" =>
AES_data (111 Downto 104) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "3" =>
AES_data (103 Downto 96) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "4" =>
AES_data (95 Downto 8

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "5" =>
AES_data (87 Downto 80) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "6" =>
AES_data (79 Downto 72) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "7" =>
AES_data (71 Downto 64) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "8" =>
AES_data (63 Downto 56) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "9" =>
AES_data (55 Downto 4

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "A" =>
AES_data (47 Downto 40) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "B" =>
AES_data (39 Downto 32) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "C" =>
AES_data (31 Downto 24) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "D" =>
AES_data (23 Downto 16) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "E" =>
AES_data (15 Downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "F" =>
AES_data (7 Downto 0) <= UART_DataOut;
toestand <= "4 X"; - ga naar toestand 4
sub_state <= "0 X";

einde geval;
end if;
- krijg de volgende byte van de gegevens
wanneer X "3" =>
indien UART_TBufE = '1 'dan - als trnsmit buffer leeg
UART_Tx <= '0 '; - in staat stellen zenden
UART_DataIn <= UART_DataOut;
toestand <= X "2";
end if;

wanneer X "4" =>
indien UART_TBufE = '1 'dan
UART_Tx <= '0 ';
UART_DataIn <= UART_DataOut;
toestand <= staat 1;
end if;

- Ontvang coderen of decoderen selecteren code
wanneer X "5" =>
UART_Rx <= '0 ';
indien UART_Outrdy = '1 'dan
indien UART_Dataout = X "31" dan
AES_mode <= '1 '; - encrypt
elsif UART_Dataout = X "32" dan
AES_mode <= '0 '; - decrypt

end if;
toestand <= staat 1;
end if;

wanneer X "6" => - verzenden aes-modus
indien UART_TBufE = '1 'dan
UART_Tx <= '0 ';
UART_DataIn <= UART_DataOut;
toestand <= staat 1;

end if;

- Ontvang Cipher Key
wanneer X "7" =>
UART_Rx <= '0 ';
belasting, <= '1 ';
if (UART_Outrdy = '1 ') then

geval sub_state is

wanneer X "0" => - sub_state
AES_key (127 Downto 120) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "1" =>
AES_key (119 Downto 112) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "2" =>
AES_key (111 Downto 104) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "3" =>
AES_key (103 Downto 96) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "4" =>
AES_key (95 Downto 8

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "5" =>
AES_key (87 Downto 80) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "6" =>
AES_key (79 Downto 72) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "7" =>
AES_key (71 Downto 64) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "8" =>
AES_key (63 Downto 56) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "9" =>
AES_key (55 Downto 4

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "A" =>
AES_key (47 Downto 40) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "B" =>
AES_key (39 Downto 32) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "C" =>
AES_key (31 Downto 24) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "D" =>
AES_key (23 Downto 16) <= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "E" =>
AES_key (15 Downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

<= UART_DataOut;
toestand <= staat 1;
sub_state <= sub_state 1;
wanneer X "F" =>
AES_key (7 Downto 0) <= UART_DataOut;
toestand <= "9 X"; - ga naar stand 9
sub_state <= "0 X";
einde geval;

end if;

- krijg de volgende byte van de belangrijkste
wanneer X "8" =>
indien UART_TBufE = '1 'dan
UART_Tx <= '0 ';
UART_DataIn <= UART_DataOut;
toestand <= "7 X";
end if;

wanneer X "9" => - staat 9
indien UART_TBufE = '1 'then - zenden buffer kosong
UART_Tx <= '0 '; - in staat stellen zenden
UART_DataIn <= UART_DataOut;
AES_start <= '1 '; - start coderen / decoderen
toestand <= staat 1;
end if;

- Cipher gedaan, zenden Ciphertext out
wanneer X "A" => - staat 10

if (UART_TBufE = '1 'en AES_Outrdy = '1') then - aes_outready
UART_Tx <= '0 ';
geval sub_state is
wanneer X "0" =>
UART_DataIn <= AES_DataOut (127 Downto 120);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "1" =>
UART_DataIn <= AES_DataOut (119 Downto 112);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "2" =>
UART_DataIn <= AES_DataOut (111 Downto 104);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "3" =>
UART_DataIn <= AES_DataOut (103 Downto 96);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "4" =>
UART_DataIn <= AES_DataOut (95 Downto 8

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

;
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "5" =>
UART_DataIn <= AES_DataOut (87 Downto 80);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "6" =>
UART_DataIn <= AES_DataOut (79 Downto 72);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "7" =>
UART_DataIn <= AES_DataOut (71 Downto 64);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "8" =>
UART_DataIn <= AES_DataOut (63 Downto 56);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "9" =>
UART_DataIn <= AES_DataOut (55 Downto 4

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

;
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "A" =>
UART_DataIn <= AES_DataOut (47 Downto 40);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "B" =>
UART_DataIn <= AES_DataOut (39 Downto 32);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "C" =>
UART_DataIn <= AES_DataOut (31 Downto 24);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "D" =>
UART_DataIn <= AES_DataOut (23 Downto 16);
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "E" =>
UART_DataIn <= AES_DataOut (15 Downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

;
sub_state <= sub_state 1;
toestand <= staat 1;
wanneer X "F" =>
UART_DataIn <= AES_DataOut (7 Downto 0);
toestand <= x "C";
sub_state <= "0 X";

einde geval;

end if;

wanneer X "B" => - state11
indien UART_TbufE = '0 'then - zenden nog niet klaar
toestand <= X "A"; - herhaal zenden
end if;

wanneer X "C" => --
toestand <= "0 X"; - herhaal
gedaan <= '1 '; - compleet zendenwanneer anderen => null;
einde geval;
end if;
einde proces FSM;einde final_aes128_arch;

dit is mijn top entiteit programma ...

 
eerste identination alles wat je moet doen om uw code.

tweede van alles wat je alleen maar hoeft te zetten clk, reset in de gevoeligheid lijst van de FSM.

 
thanx voor het antwoord!
dus je bedoelt dat ik nodig clk zetten en opnieuw alleen in een FSM staat die gevoelig zijn voor beide ... Ik zal proberen ...

 
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