A
Augustus
Guest
Hoe schrijf verilog code voor de FPGA input te ontvangen van de computer toetsenbord via RS-232
Is dit juist?
module serialfun (CLK, RxD, TxD, GPout, GPin);
input clk;
input RxD;
uitgang TxD;
output [7:0] GPout;
input [7:0] GPin;
////////////////////////////////////////////////// /
draad RxD_data_ready; draad [7:0] RxD_data;
async_receiver deserializer (. CLK (CLK),. RxD (RxD),. RxD_data_ready (RxD_data_ready),. RxD_data (RxD_data));
reg [7:0] GPout;
altijd @ (posedge clk) if (RxD_data_ready) GPout <= RxD_data;
////////////////////////////////////////////////// /
async_transmitter serializer (. CLK (CLK),. TxD (TxD),. TxD_start (RxD_data_ready),. TxD_data (GPin));
endmodule
Is dit juist?
module serialfun (CLK, RxD, TxD, GPout, GPin);
input clk;
input RxD;
uitgang TxD;
output [7:0] GPout;
input [7:0] GPin;
////////////////////////////////////////////////// /
draad RxD_data_ready; draad [7:0] RxD_data;
async_receiver deserializer (. CLK (CLK),. RxD (RxD),. RxD_data_ready (RxD_data_ready),. RxD_data (RxD_data));
reg [7:0] GPout;
altijd @ (posedge clk) if (RxD_data_ready) GPout <= RxD_data;
////////////////////////////////////////////////// /
async_transmitter serializer (. CLK (CLK),. TxD (TxD),. TxD_start (RxD_data_ready),. TxD_data (GPin));
endmodule