C
cdic
Guest
Schematische Capture: Design-Bouwkunde
HDL Entry: Summit, HDL Designer Series
HDL Analyzer: Debussy
RTL Simulatie: LDV, VCS, Modelsim
Synthese: Design-Compiler
STA: Prime Time
ATPG: Tetra-Max
Niveau Transitor Simulatie: Hspice
Analyzer (Full chip): Hsim, Math TA
P & R: Magma
Layout editor: IC-station, Panda2000
Layout Verificatie: Calibre, Panda2000
Extractie: xCalibre
HDL Entry: Summit, HDL Designer Series
HDL Analyzer: Debussy
RTL Simulatie: LDV, VCS, Modelsim
Synthese: Design-Compiler
STA: Prime Time
ATPG: Tetra-Max
Niveau Transitor Simulatie: Hspice
Analyzer (Full chip): Hsim, Math TA
P & R: Magma
Layout editor: IC-station, Panda2000
Layout Verificatie: Calibre, Panda2000
Extractie: xCalibre