fout in VHDL-real???

M

meemee2

Guest
FOUT: XST: 1547 - D: / watch/iseexamples/filter/filter1.vhd lijn 15: Signaal <x> van het type onroerend wordt niet ondersteund.
FOUT: XST mislukt

- Filter Instellingen:
--
- Discrete-Time FIR filter (real)
- -------------------------------
- Filter Structuur: Direct-Form FIR
- Filter Order: 50
- Stabiel: Ja
- Lineaire Fase: Ja (type 1)
- ------------------------------------------------ -------------
LIBRARY IEEE;
GEBRUIK IEEE.std_logic_1164.all;
GEBRUIK IEEE.numeric_std.ALL;

ENTITY filter
PORT :) CLK IN std_logic;
clk_enable: IN std_logic;
reset: IN std_logic;filter_in: In het echte; - dubbel
);

filter_out: OUT Real - double);END filter;-------------------------------------------------- --------------
- Module Architecture: filter
-------------------------------------------------- --------------
ARCHITECTUUR VAN RTL filter
- Lokale Functies
- Type Definities
TYPE delay_pipeline_type IS ARRAY (natural range <>) van reële; - dubbel
- Constanten
CONSTANT coeff1: real: =-9.1909820846825603E-004; - dubbel
CONSTANT coeff2: real: =-2.7176960265955000E-003; - dubbel
CONSTANT coeff3: real: =-2.4869527598323101E-003; - dubbel
CONSTANT coeff4: real: = 3.6614383835070902E-003; - dubbele
CONSTANT coeff5: real: = 1.3650925230662400E-002; - dubbele
CONSTANT coeff6: real: = 1.7351165901093299E-002; - dubbele
CONSTANT coeff7: real: = 7.6653061904216804E-003; - dubbele
CONSTANT coeff8: real: =-6.5547188696423999E-003; - dubbel
CONSTANT coeff9: real: =-7.6967840370653602E-003; - dubbel
CONSTANT coeff10: real: = 6.1054594213943601E-003; - dubbele
CONSTANT coeff11: real: = 1.3873915748635401E-002; - dubbele
CONSTANT coeff12: real: = 3.5086172829091000E-004; - dubbele
CONSTANT coeff13: real: =-1.6908925436690501E-002; - dubbel
CONSTANT coeff14: real: =-8.9056427491586796E-003; - dubbel
CONSTANT coeff15: real: = 1.7441129500854899E-002; - dubbele
CONSTANT coeff16: real: = 2.0745044527609901E-002; - dubbele
CONSTANT coeff17: real: =-1.2296494251940300E-002; - dubbel
CONSTANT coeff18: real: =-3.4240865909578401E-002; - dubbel
CONSTANT coeff19: real: =-1.0345296055723999E-003; - dubbel
CONSTANT coeff20: real: = 4.7790305520801497E-002; - dubbele
CONSTANT coeff21: real: = 2.7363037914847999E-002; - dubbele
CONSTANT coeff22: real: =-5.9379518831046599E-002; - dubbel
CONSTANT coeff23: real: =-8.2307025929229102E-002; - dubbel
CONSTANT coeff24: real: = 6.7186909432870506E-002; - dubbele
CONSTANT coeff25: real: = 3.1001517709025100E-001; - dubbele
CONSTANT coeff26: real: = 4.3004788034351699E-001; - dubbele
CONSTANT coeff27: real: = 3.1001517709025100E-001; - dubbele
CONSTANT coeff28: real: = 6.7186909432870506E-002; - dubbele
CONSTANT coeff29: real: =-8.2307025929229102E-002; - dubbel
CONSTANT coeff30: real: =-5.9379518831046599E-002; - dubbel
CONSTANT coeff31: real: = 2.7363037914847999E-002; - dubbele
CONSTANT coeff32: real: = 4.7790305520801497E-002; - dubbele
CONSTANT coeff33: real: =-1.0345296055723999E-003; - dubbel
CONSTANT coeff34: real: =-3.4240865909578401E-002; - dubbel
CONSTANT coeff35: real: =-1.2296494251940300E-002; - dubbel
CONSTANT coeff36: real: = 2.0745044527609901E-002; - dubbele
CONSTANT coeff37: real: = 1.7441129500854899E-002; - dubbele
CONSTANT coeff38: real: =-8.9056427491586796E-003; - dubbel
CONSTANT coeff39: real: =-1.6908925436690501E-002; - dubbel
CONSTANT coeff40: real: = 3.5086172829091000E-004; - dubbele
CONSTANT coeff41: real: = 1.3873915748635401E-002; - dubbele
CONSTANT coeff42: real: = 6.1054594213943601E-003; - dubbele
CONSTANT coeff43: real: =-7.6967840370653602E-003; - dubbel
CONSTANT coeff44: real: =-6.5547188696423999E-003; - dubbel
CONSTANT coeff45: real: = 7.6653061904216804E-003; - dubbele
CONSTANT coeff46: real: = 1.7351165901093299E-002; - dubbele
CONSTANT coeff47: real: = 1.3650925230662400E-002; - dubbele
CONSTANT coeff48: real: = 3.6614383835070902E-003; - dubbele
CONSTANT coeff49: real: =-2.4869527598323101E-003; - dubbel
CONSTANT coeff50: real: =-2.7176960265955000E-003; - dubbel
CONSTANT coeff51: real: =-9.1909820846825603E-004; - dubbel

- Signalen
SIGNAL delay_pipeline: delay_pipeline_type (0 tot 50): = (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0,0); - dubbel
SIGNAL product51: real: = 0.0; - dubbel
SIGNAL product50: real: = 0.0; - dubbel
SIGNAL product49: real: = 0.0; - dubbel
SIGNAL product48: real: = 0.0; - dubbel
SIGNAL product47: real: = 0.0; - dubbel
SIGNAL product46: real: = 0.0; - dubbel
SIGNAL product45: real: = 0.0; - dubbel
SIGNAL product44: real: = 0.0; - dubbel
SIGNAL product43: real: = 0.0; - dubbel
SIGNAL product42: real: = 0.0; - dubbel
SIGNAL product41: real: = 0.0; - dubbel
SIGNAL product40: real: = 0.0; - dubbel
SIGNAL product39: real: = 0.0; - dubbel
SIGNAL product38: real: = 0.0; - dubbel
SIGNAL product37: real: = 0.0; - dubbel
SIGNAL product36: real: = 0.0; - dubbel
SIGNAL product35: real: = 0.0; - dubbel
SIGNAL product34: real: = 0.0; - dubbel
SIGNAL product33: real: = 0.0; - dubbel
SIGNAL product32: real: = 0.0; - dubbel
SIGNAL product31: real: = 0.0; - dubbel
SIGNAL product30: real: = 0.0; - dubbel
SIGNAL product29: real: = 0.0; - dubbel
SIGNAL product28: real: = 0.0; - dubbel
SIGNAL product27: real: = 0.0; - dubbel
SIGNAL product26: real: = 0.0; - dubbel
SIGNAL product25: real: = 0.0; - dubbel
SIGNAL product24: real: = 0.0; - dubbel
SIGNAL product23: real: = 0.0; - dubbel
SIGNAL product22: real: = 0.0; - dubbel
SIGNAL product21: real: = 0.0; - dubbel
SIGNAL product20: real: = 0.0; - dubbel
SIGNAL product19: real: = 0.0; - dubbel
SIGNAL product18: real: = 0.0; - dubbel
SIGNAL product17: real: = 0.0; - dubbel
SIGNAL product16: real: = 0.0; - dubbel
SIGNAL product15: real: = 0.0; - dubbel
SIGNAL product14: real: = 0.0; - dubbel
SIGNAL product13: real: = 0.0; - dubbel
SIGNAL product12: real: = 0.0; - dubbel
SIGNAL product11: real: = 0.0; - dubbel
SIGNAL product10: real: = 0.0; - dubbel
SIGNAL product9: real: = 0.0; - dubbel
SIGNAL product8: real: = 0.0; - dubbel
SIGNAL product7: real: = 0.0; - dubbel
SIGNAL product6: real: = 0.0; - dubbel
SIGNAL product5: real: = 0.0; - dubbel
SIGNAL Product4: real: = 0.0; - dubbel
SIGNAL Product3: real: = 0.0; - dubbel
SIGNAL product2: real: = 0.0; - dubbel
SIGNAL product1: real: = 0.0; - dubbel
SIGNAL sum1: real: = 0.0; - dubbel
SIGNAL sum2: real: = 0.0; - dubbel
SIGNAL sum3: real: = 0.0; - dubbel
SIGNAL sum4: real: = 0.0; - dubbel
SIGNAL sum5: real: = 0.0; - dubbel
SIGNAL sum6: real: = 0.0; - dubbel
SIGNAL sum7: real: = 0.0; - dubbel
SIGNAL sum8: real: = 0.0; - dubbel
SIGNAL sum9: real: = 0.0; - dubbel
SIGNAL sum10: real: = 0.0; - dubbel
SIGNAL sum11: real: = 0.0; - dubbel
SIGNAL sum12: real: = 0.0; - dubbel
SIGNAL sum13: real: = 0.0; - dubbel
SIGNAL sum14: real: = 0.0; - dubbel
SIGNAL sum15: real: = 0.0; - dubbel
SIGNAL sum16: real: = 0.0; - dubbel
SIGNAL sum17: real: = 0.0; - dubbel
SIGNAL sum18: real: = 0.0; - dubbel
SIGNAL sum19: real: = 0.0; - dubbel
SIGNAL sum20: real: = 0.0; - dubbel
SIGNAL sum21: real: = 0.0; - dubbel
SIGNAL sum22: real: = 0.0; - dubbel
SIGNAL sum23: real: = 0.0; - dubbel
SIGNAL sum24: real: = 0.0; - dubbel
SIGNAL sum25: real: = 0.0; - dubbel
SIGNAL sum26: real: = 0.0; - dubbel
SIGNAL sum27: real: = 0.0; - dubbel
SIGNAL sum28: real: = 0.0; - dubbel
SIGNAL sum29: real: = 0.0; - dubbel
SIGNAL sum30: real: = 0.0; - dubbel
SIGNAL sum31: real: = 0.0; - dubbel
SIGNAL sum32: real: = 0.0; - dubbel
SIGNAL sum33: real: = 0.0; - dubbel
SIGNAL sum34: real: = 0.0; - dubbel
SIGNAL sum35: real: = 0.0; - dubbel
SIGNAL sum36: real: = 0.0; - dubbel
SIGNAL sum37: real: = 0.0; - dubbel
SIGNAL sum38: real: = 0.0; - dubbel
SIGNAL sum39: real: = 0.0; - dubbel
SIGNAL sum40: real: = 0.0; - dubbel
SIGNAL Sum41: real: = 0.0; - dubbel
SIGNAL sum42: real: = 0.0; - dubbel
SIGNAL sum43: real: = 0.0; - dubbel
SIGNAL sum44: real: = 0.0; - dubbel
SIGNAL sum45: real: = 0.0; - dubbel
SIGNAL sum46: real: = 0.0; - dubbel
SIGNAL sum47: real: = 0.0; - dubbel
SIGNAL sum48: real: = 0.0; - dubbel
SIGNAL sum49: real: = 0.0; - dubbel
SIGNAL sum50: real: = 0.0; - dubbel
SIGNAL output_register: real: = 0.0; - dubbelBEGIN

- Block Verklaringen
Delay_Pipeline_process: PROCES (clk, reset)
BEGIN
IF reset = '1 'THEN
delay_pipeline (0 tot 50) <= (OVERIG => 0.0000000000000000E 000);
Elsif clk'event en CLK = '1 'THEN
IF clk_enable = '1 'THEN
delay_pipeline (0) <= filter_in;
delay_pipeline (1 tot 50) <= delay_pipeline (0 tot 49);
END IF;
END IF;
Proces beëindigen Delay_Pipeline_process;

product51 <= delay_pipeline (50) * coeff51;

product50 <= delay_pipeline (49) * coeff50;

product49 <= delay_pipeline (4

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

* Coeff49;

product48 <= delay_pipeline (47) * coeff48;

product47 <= delay_pipeline (46) * coeff47;

product46 <= delay_pipeline (45) * coeff46;

product45 <= delay_pipeline (44) * coeff45;

product44 <= delay_pipeline (43) * coeff44;

product43 <= delay_pipeline (42) * coeff43;

product42 <= delay_pipeline (41) * coeff42;

product41 <= delay_pipeline (40) * coeff41;

product40 <= delay_pipeline (39) * coeff40;

product39 <= delay_pipeline (3

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

* Coeff39;

product38 <= delay_pipeline (37) * coeff38;

product37 <= delay_pipeline (36) * coeff37;

product36 <= delay_pipeline (35) * coeff36;

product35 <= delay_pipeline (34) * coeff35;

product34 <= delay_pipeline (33) * coeff34;

product33 <= delay_pipeline (32) * coeff33;

product32 <= delay_pipeline (31) * coeff32;

product31 <= delay_pipeline (30) * coeff31;

product30 <= delay_pipeline (29) * coeff30;

product29 <= delay_pipeline (2

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

* Coeff29;

product28 <= delay_pipeline (27) * coeff28;

product27 <= delay_pipeline (26) * coeff27;

product26 <= delay_pipeline (25) * coeff26;

product25 <= delay_pipeline (24) * coeff25;

product24 <= delay_pipeline (23) * coeff24;

product23 <= delay_pipeline (22) * coeff23;

product22 <= delay_pipeline (21) * coeff22;

product21 <= delay_pipeline (20) * coeff21;

product20 <= delay_pipeline (19) * coeff20;

product19 <= delay_pipeline (1

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

* Coeff19;

product18 <= delay_pipeline (17) * coeff18;

product17 <= delay_pipeline (16) * coeff17;

product16 <= delay_pipeline (15) * coeff16;

product15 <= delay_pipeline (14) * coeff15;

product14 <= delay_pipeline (13) * coeff14;

product13 <= delay_pipeline (12) * coeff13;

product12 <= delay_pipeline (11) * coeff12;

product11 <= delay_pipeline (10) * coeff11;

product10 <= delay_pipeline (9) * coeff10;

product9 <= delay_pipeline (

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

* Coeff9;

product8 <= delay_pipeline (7) * coeff8;

product7 <= delay_pipeline (6) * coeff7;

product6 <= delay_pipeline (5) * coeff6;

product5 <= delay_pipeline (4) * coeff5;

Product4 <= delay_pipeline (3) * coeff4;

Product3 <= delay_pipeline (2) * coeff3;

product2 <= delay_pipeline (1) * coeff2;

product1 <= delay_pipeline (0) * coeff1;

sum1 <= product1 product2;

sum2 <= sum1 Product3;

sum3 <= sum2 Product4;

sum4 <= sum3 product5;

sum5 <= sum4 product6;

sum6 <= sum5 product7;

sum7 <= sum6 product8;

sum8 <= sum7 product9;

sum9 <= sum8 product10;

sum10 <= sum9 product11;

sum11 <= sum10 product12;

sum12 <= sum11 product13;

sum13 <= sum12 product14;

sum14 <= sum13 product15;

sum15 <= sum14 product16;

sum16 <= sum15 product17;

sum17 <= sum16 product18;

sum18 <= sum17 product19;

sum19 <= sum18 product20;

sum20 <= sum19 product21;

sum21 <= sum20 product22;

sum22 <= sum21 product23;

sum23 <= sum22 product24;

sum24 <= sum23 product25;

sum25 <= sum24 product26;

sum26 <= sum25 product27;

sum27 <= sum26 product28;

sum28 <= sum27 product29;

sum29 <= sum28 product30;

sum30 <= sum29 product31;

sum31 <= sum30 product32;

sum32 <= sum31 product33;

sum33 <= sum32 product34;

sum34 <= sum33 product35;

sum35 <= sum34 product36;

sum36 <= sum35 product37;

sum37 <= sum36 product38;

sum38 <= sum37 product39;

sum39 <= sum38 product40;

sum40 <= sum39 product41;

Sum41 <= sum40 product42;

sum42 <= Sum41 product43;

sum43 <= sum42 product44;

sum44 <= sum43 product45;

sum45 <= sum44 product46;

sum46 <= sum45 product47;

sum47 <= sum46 product48;

sum48 <= sum47 product49;

sum49 <= sum48 product50;

sum50 <= sum49 product51;

Output_Register_process: PROCES (clk, reset)
BEGIN
IF reset = '1 'THEN
output_register <= 0.0000000000000000E 000;
Elsif clk'event en CLK = '1 'THEN
IF clk_enable = '1 'THEN
output_register <= sum50;
END IF;
END IF;
Proces beëindigen Output_Register_process;

- Toekenningsopdrachten
filter_out <= output_register;

END rtl;

 
kan iemand me helpen met de VHDL-code.?is gerentor door Matlab ..
een filter ...
de fout hoogtepunt in ROOD ...
Thanks in advance

 
Ik weet niet veel over VHDL, maar de woorden "echte dubbel" en "XST" niet mengen.XST ondersteunt geen floating point rekenkunde.
Last edited by echo47 op 21 okt 2004 10:20; bewerkten in totaal 1 keer

 
Hoi,

Ik zie dat je probeert te synthetiseren met XST een entiteit met 'echte' ports ...niet goed m8.

Dus wat denk je dat de synthesizer zal doen?

<img src="http://www.edaboard.com/images/smiles/icon_confused.gif" alt="Confused" border="0" />Synthesizers niet realen ondersteunen, althans XST niet, kan misschien Precision of Synplify uitzoeken hoe diep je wilt dat de haven te zijn en dwang aan 32 bits ...hoewel ik niet denk het niet.

Dus het is een afweging tussen de resolutie (hoe nauwkeurig je wilt dat uw 'echte' te zijn) en het aantal poorten (effecten) die u wilt gebruiken in je FPGA / CPLD.Je moet bedenken dat en vervolgens converteren deel uw onroerend naar 'std_logic_vector' echte & 'deel std_logic_vector' decimaal.

- maestor

 
deel je echte converteren naar 'std_logic_vector' echte & 'deel std_logic_vector' --
bedoel je t

 
deel je echte converteren naar 'std_logic_vector' echte & 'deel std_logic_vector' --
bedoel je dat verandering echt te std_logic_vector.
en alle
CONSTANT coeff1: real: =-9.1909820846825603E-004; - dubbel
CONSTANT coeff2: real: =-2.7176960265955000E-003; - dubbel
CONSTANT coeff3: real: =-2.4869527598323101E-003; - dubbel
CONSTANT coeff4: real: = 3.6614383835070902E-003; - dubbele
CONSTANT coeff5: real: = 1.3650925230662400E-002; - dubbele
CONSTANT coeff6: real: = 1.7351165901093299E-002; - dubbele
tp decimaal getal?
bedankt

 
He, ik denk dat het zal een compilatie fout te produceren.
Ik denk dat je moet veranderen

filter_out: OUT Real - double); -> filter_out: OUT real); - double

Ik denk dat '); "wordt behandeld als een onderdeel van een commentaar in je code.

 
hi all.
i met hetzelfde probleem geconfronteerd, terwijl de synthese van VHDL-code gegenereerd door mathlab toolbox
fdatools
Ik denk dat dit nogal bug voor Matlab synthese met Altera qu (at) rtus software ..
kan iemand oplossing biedt ..
opmerkingen.deze oplossing gepost op deze pagina ..ive geprobeerd ..
it doesnt work ..
bedankt al op voorhand

 
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