D
darshankumar
Guest
Code:
`tijdschaal 1ns / 1PS module sd (input clk, ingang nl, ingang [07:00] DIN1, ingang [07:00] addr1, input die we, output [07:00] DOUT1); parameter RAM_WIDTH = 8; parameter RAM_ADDR_BITS = 8; reg [RAM_WIDTH-1: 0] Bram [(2 ** RAM_ADDR_BITS) -1:0]; draad [07:00] DOUT1; altijd @ (posedge CLK) if (nl) beginnen als (wij) bram [addr1]