dumpingcode geheugen Verilog naar VHDL

[karper1986]

Please help me in de vertaling van deze Verilog naar VHDL

taak dump_dmem;
integer i;

integer fdmem0;
integer fdmem1;
integer fdmem2;
integer fdmem3;
integer fdmem4;
integer fdmem5;
integer fdmem6;
integer fdmem7;

reg [31:0] dmemw0;
reg [31:0] dmemw1;
reg [31:0] dmemw2;
reg [31:0] dmemw3;
reg [31:0] dmemw4;
reg [31:0] dmemw5;
reg [31:0] dmemw6;
reg [31:0] dmemw7;

beginnen

fdmem0 = $ fopen ( "FFT_DMEM0_DUMP);
fdmem1 = $ fopen ( "FFT_DMEM1_DUMP);
fdmem2 = $ fopen ( "FFT_DMEM2_DUMP);
fdmem3 = $ fopen ( "FFT_DMEM3_DUMP);
fdmem4 = $ fopen ( "FFT_DMEM4_DUMP);
fdmem5 = $ fopen ( "FFT_DMEM5_DUMP);
fdmem6 = $ fopen ( "FFT_DMEM6_DUMP);
fdmem7 = $ fopen ( "FFT_DMEM7_DUMP);

for (i = 0; i <(

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Koel" border="0" />

, I = i 1)

beginnen
dmemw0 = memory0.memory ;
dmemw1 = memory1.memory ;
dmemw2 = memory2.memory ;
dmemw3 = memory3.memory ;
dmemw4 = memory4.memory ;
dmemw5 = memory5.memory ;
dmemw6 = memory6.memory ;
dmemw7 = memory7.memory ;

$ fdisplay (fdmem0, "% d \ n", dmemw0);
$ fdisplay (fdmem1, "% d \ n", dmemw1);
$ fdisplay (fdmem2, "% d \ n", dmemw2);
$ fdisplay (fdmem3, "% d \ n", dmemw3);
$ fdisplay (fdmem4, "% d \ n", dmemw4);
$ fdisplay (fdmem5, "% d \ n", dmemw5);
$ fdisplay (fdmem6, "% d \ n", dmemw6);
$ fdisplay (fdmem7, "% d \ n", dmemw7);
eindigen

$ fclose (fdmem0);
$ fclose (fdmem1);
$ fclose (fdmem2);
$ fclose (fdmem3);
$ fclose (fdmem4);
$ fclose (fdmem5);
$ fclose (fdmem6);
$ fclose (fdmem7);

eindigen
endtask

Thanks a lot.